*+.High-Level Synthesizer Sister
Project.
Sister is high-level synthesizer for SoC design .
It reads SystemC source code and creates Verilog HDL source code.
It reads SystemC source code and creates Verilog HDL source code.
Developer.
License.
BSD Style License
Download.
Contact.
support[at]ktds.co.jp
Copyright(c) Sister. All Rights Reserved.